Multiplication of Complex Numbers Represented in Floating Point

ABSTRACT

A multiplier circuit that operates on a novel complex data format where the real and imaginary parts of the source and result operands are represented by single precision floating point numbers. The invention provides direct support for complex numbers in floating point representation, thus reducing the number of instructions and processor cycles with improved performance.

CLAIM OF PRIORITY

This application claims priority under 35 USC 119(e) (1) to U.S. Provisional Application No. 61/387,367 filed Sep. 28, 2010.

TECHNICAL FIELD OF THE INVENTION

This invention relates in general to the field of computing systems and more particularly to arithmetic processing units.

BACKGROUND OF THE INVENTION

High performance Digital Signal Processors (DSP) require the flexibility to operate on many different formats of data. Data may be integer fixed point data—signed or unsigned, real or complex, 32-bit, 16-bit or 8-bit. Or it may be floating point data—single-precision real, single-precision complex, or double precision.

A number of algorithms are dominated by complex linear algebra, and the efficient processing of complex numbers is extremely important. An additional requirement is a wide dynamic range that may exceed the range available in the 32 bit data type.

SUMMARY OF THE INVENTION

This invention defines a data type to represent complex numbers which consists of two single precision floating point numbers. One floating point number represents the real portion, and the second floating point number represents the imaginary portion. An instruction is defined that can be used to multiply two complex numbers in an efficient manner.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of this invention are illustrated in the drawings, in which:

FIG. 1 illustrates the organization of a typical digital signal processor to which this invention is applicable (prior art);

FIG. 2 illustrates details of a very long instruction word digital signal processor core suitable for use in FIG. 1 (prior art);

FIG. 3 illustrates the pipeline stages of the very long instruction word digital signal processor core illustrated in FIG. 2 (prior art);

FIG. 4 illustrates the instruction syntax of the very long instruction word digital signal processor core illustrated in FIG. 2 (prior art);

FIG. 5 illustrates one embodiment of the invention;

FIG. 6 shows a second embodiment and

FIG. 7 illustrates a third embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates the organization of a typical digital signal processor system 100 to which this invention is applicable (prior art). Digital signal processor system 100 includes central processing unit core 110. Central processing unit core 110 includes the data processing portion of digital signal processor system 100. Central processing unit core 110 could be constructed as known in the art and would typically includes a register file, an integer arithmetic logic unit, an integer multiplier and program flow control units. An example of an appropriate central processing unit core is described below in conjunction with FIGS. 2 to 4.

Digital signal processor system 100 includes a number of cache memories. FIG. 1 illustrates a pair of first level caches. Level one instruction cache (L1I) 121 stores instructions used by central processing unit core 110. Central processing unit core 110 first attempts to access any instruction from level one instruction cache 121. Level one data cache (L1D) 123 stores data used by central processing unit core 110. Central processing unit core 110 first attempts to access any required data from level one data cache 123. The two level one caches are backed by a level two unified cache (L2) 130. In the event of a cache miss to level one instruction cache 121 or to level one data cache 123, the requested instruction or data is sought from level two unified cache 130. If the requested instruction or data is stored in level two unified cache 130, then it is supplied to the requesting level one cache for supply to central processing unit core 110. As is known in the art, the requested instruction or data may be simultaneously supplied to both the requesting cache and central processing unit core 110 to speed use.

Level two unified cache 130 is further coupled to higher level memory systems. Digital signal processor system 100 may be a part of a multiprocessor system. The other processors of the multiprocessor system are coupled to level two unified cache 130 via a transfer request bus 141 and a data transfer bus 143. A direct memory access unit 150 provides the connection of digital signal processor system 100 to external memory 161 and external peripherals 169.

FIG. 2 is a block diagram illustrating details of a digital signal processor integrated circuit 200 suitable but not essential for use in this invention (prior art). The digital signal processor integrated circuit 200 includes central processing unit 1, which is a 32-bit eight-way VLIW pipelined processor. Central processing unit 1 is coupled to level one instruction cache 121 included in digital signal processor integrated circuit 200. Digital signal processor integrated circuit 200 also includes level one data cache 123. Digital signal processor integrated circuit 200 also includes peripherals 4 to 9. These peripherals preferably include an external memory interface (EMIF) 4 and a direct memory access (DMA) controller 5. External memory interface (EMIF) 4 preferably supports access to supports synchronous and asynchronous SRAM and synchronous DRAM. Direct memory access (DMA) controller 5 preferably provides 2-channel auto-boot loading direct memory access. These peripherals include power-down logic 6. Power-down logic 6 preferably can halt central processing unit activity, peripheral activity, and phase lock loop (PLL) clock synchronization activity to reduce power consumption. These peripherals also include host ports 7, serial ports 8 and programmable timers 9.

Central processing unit 1 has a 32-bit, byte addressable address space. Internal memory on the same integrated circuit is preferably organized in a data space including level one data cache 123 and a program space including level one instruction cache 121. When off-chip memory is used, preferably these two spaces are unified into a single memory space via the external memory interface (EMIF) 4.

Level one data cache 123 may be internally accessed by central processing unit 1 via two internal ports 3 a and 3 b. Each internal port 3 a and 3 b preferably has 32 bits of data and a 32-bit byte address reach. Level one instruction cache 121 may be internally accessed by central processing unit 1 via a single port 2 a. Port 2 a of level one instruction cache 121 preferably has an instruction-fetch width of 256 bits and a 30-bit word (four bytes) address, equivalent to a 32-bit byte address.

Central processing unit 1 includes program fetch unit 10, instruction dispatch unit 11, instruction decode unit 12 and two data paths 20 and 30. First data path 20 includes four functional units designated L1 unit 22, S1 unit 23, M1 unit 24 and D1 unit 25 and 16 32-bit A registers forming register file 21. Second data path 30 likewise includes four functional units designated L2 unit 32, S2 unit 33, M2 unit 34 and D2 unit 35 and 16 32-bit B registers forming register file 31. The functional units of each data path access the corresponding register file for their operands. There are two cross paths 27 and 37 permitting access to one register in the opposite register file each pipeline stage. Central processing unit 1 includes control registers 13, control logic 14, test logic 15, emulation logic 16 and interrupt logic 17.

Program fetch unit 10, instruction dispatch unit 11 and instruction decode unit 12 recall instructions from level one instruction cache 121 and deliver up to eight 32-bit instructions to the functional units every instruction cycle. Processing occurs simultaneously in each of the two data paths 20 and 30. As previously described each data path has four corresponding functional units (L, S, M and D) and a corresponding register file containing 16 32-bit registers. Each functional unit is controlled by a 32-bit instruction. The data paths are further described below. A control register file 13 provides the means to configure and control various processor operations.

FIG. 3 illustrates the pipeline stages 300 of digital signal processor core 110 (prior art). These pipeline stages are divided into three groups: fetch group 310; decode group 320; and execute group 330. All instructions in the instruction set flow through the fetch, decode, and execute stages of the pipeline. Fetch group 310 has four phases for all instructions, and decode group 320 has two phases for all instructions. Execute group 330 requires a varying number of phases depending on the type of instruction.

The fetch phases of the fetch group 310 are: Program address generate phase 311 (PG); Program address send phase 312 (PS); Program access ready wait stage 313 (PW); and Program fetch packet receive stage 314 (PR). Digital signal processor core 110 uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed through fetch group 310 together. During PG phase 311, the program address is generated in program fetch unit 10. During PS phase 312, this program address is sent to memory. During PW phase 313, the memory read occurs. Finally during PR phase 314, the fetch packet is received at CPU 1.

The decode phases of decode group 320 are: Instruction dispatch (DP) 321; and Instruction decode (DC) 322. During the DP phase 321, the fetch packets are split into execute packets. Execute packets consist of one or more instructions which are coded to execute in parallel. During DP phase 322, the instructions in an execute packet are assigned to the appropriate functional units. Also during DC phase 322, the source registers, destination registers and associated paths are decoded for the execution of the instructions in the respective functional units.

The execute phases of the execute group 330 are: Execute (E1) 331; Execute 2 (E2) 332; Execute 3 (E3) 333; Execute 4 (E4) 334; and Execute 5 (E5) 335. Different types of instructions require different numbers of these phases to complete. These phases of the pipeline play an important role in understanding the device state at CPU cycle boundaries.

During E1 phase 331, the conditions for the instructions are evaluated and operands are read for all instruction types. For load and store instructions, address generation is performed and address modifications are written to a register file. For branch instructions, branch fetch packet in PG phase 311 is affected. For all single-cycle instructions, the results are written to a register file. All single-cycle instructions complete during the E1 phase 331.

During the E2 phase 332, for load instructions, the address is sent to memory. For store instructions, the address and data are sent to memory. Single-cycle instructions that saturate results set the SAT bit in the control status register (CSR) if saturation occurs. For single cycle 16 by 16 multiply instructions, the results are written to a register file. For M unit non-multiply instructions, the results are written to a register file. All ordinary multiply unit instructions complete during E2 phase 322.

During E3 phase 333, data memory accesses are performed. Any multiply instruction that saturates results sets the SAT bit in the control status register (CSR) if saturation occurs. Store instructions complete during the E3 phase 333.

During E4 phase 334, for load instructions, data is brought to the CPU boundary. For multiply extension instructions, the results are written to a register file. Multiply extension instructions complete during the E4 phase 334.

During E5 phase 335, load instructions write data into a register. Load instructions complete during the E5 phase 335.

FIG. 4 illustrates an example of the instruction coding of instructions used by digital signal processor core 110 (prior art). Each instruction consists of 32 bits and controls the operation of one of the eight functional units. The bit fields are defined as follows. The creg field (bits 29 to 31) is the conditional register field. These bits identify whether the instruction is conditional and identify the predicate register. The z bit (bit 28) indicates whether the predication is based upon zero or not zero in the predicate register. If z=1, the test is for equality with zero. If z=0, the test is for nonzero. The case of creg=0 and z=0 is treated as always true to allow unconditional instruction execution. The creg field is encoded in the instruction opcode as shown in Table 1.

TABLE 1 Conditional creg z Register 31 30 29 28 Unconditional 0 0 0 0 Reserved 0 0 0 1 B0 0 0 1 z B1 0 1 0 z B2 0 1 1 z A1 1 0 0 z A2 1 0 1 z A0 1 1 0 z Reserved 1 1 1 x

Note that “z” in the z bit column refers to the zero/not zero comparison selection noted above and “x” is a don't care state. This coding can only specify a subset of the 32 registers in each register file as predicate registers. This selection was made to preserve bits in the instruction coding.

The dst field (bits 23 to 27) specifies one of the 32 registers in the corresponding register file as the destination of the instruction results.

The scr2 field (bits 18 to 22) specifies one of the 32 registers in the corresponding register file as the second source operand.

The scr1/cst field (bits 13 to 17) has several meanings depending on the instruction opcode field (bits 3 to 12). The first meaning specifies one of the 32 registers of the corresponding register file as the first operand. The second meaning is a 5-bit immediate constant. Depending on the instruction type, this is treated as an unsigned integer and zero extended to 32 bits or is treated as a signed integer and sign extended to 32 bits. Lastly, this field can specify one of the 32 registers in the opposite register file if the instruction invokes one of the register file cross paths 27 or 37.

The opcode field (bits 3 to 12) specifies the type of instruction and designates appropriate instruction options. A detailed explanation of this field is beyond the scope of this invention except for the instruction options detailed below.

The s bit (bit 1) designates the data path 20 or 30. If s=0, then data path 20 is selected. This limits the functional unit to L1 unit 22, S1 unit 23, M1 unit 24 and D1 unit 25 and the corresponding register file A 21. Similarly, s=1 selects data path 20 limiting the functional unit to L2 unit 32, S2 unit 33, M2 unit 34 and D2 unit 35 and the corresponding register file B 31.

The p bit (bit 0) marks the execute packets. The p-bit determines whether the instruction executes in parallel with the following instruction. The p-bits are scanned from lower to higher address. If p=1 for the current instruction, then the next instruction executes in parallel with the current instruction. If p=0 for the current instruction, then the next instruction executes in the cycle after the current instruction. All instructions executing in parallel constitute an execute packet. An execute packet can contain up to eight instructions. Each instruction in an execute packet must use a different functional unit.

Additional instructions need to be implemented for efficient floating point calculations. This invention implements an efficient method of multiplying complex numbers, particularly in applications where the dynamic range of the required computations exceeds the range available in the standard 32-bit floating point data type.

A new data type is defined to represent complex numbers which consists of two single precision floating point numbers. One floating point number represents the real portion, and the other floating point number represents the imaginary portion of the operands.

One embodiment is shown on FIG. 5, which is a straight multiply between two complex numbers SRC1 and SRC2. Register 501 holds the real part of SRC1, and register 502 holds the imaginary part of SRC1. Similarly, the real part of SRC2 is held in register 503, and the imaginary part is in register 504. As shown on FIG. 5, the real part of SRC1 is multiplied by the real part of SRC2, and the imaginary part of SRC1 is multiplied by the imaginary part of SRC2 using floating point multipliers 505 through 508. The real part of the result (511) is derived by subtracting the result of multiplier 506 from multiplier 505 using floating point subtract circuit 509, and the imaginary part of the result (512) is formed by adding the results of multipliers 507 and 508 using the floating point adder 510.

If floating point subtract circuit 509 and floating point adder 510 is swapped the result will be the complex conjugate of one operand. If the src1 operand is conjugated, then the result of src1_imag*src2_real will be the number which is subtracted from src1_real*src2_imag. Likewise, if src2 were conjugated, then src1_real*src2_imag is subtracted from src1_imag*src2_real.

An other implementation is shown on FIG. 6 which performs SRC1*SRC2*j (where src1 and src2 are complex floating point numbers) and operates in the same manner as the above, with the exception that the real and imaginary portions of the result are swapped, and the new real result has it's sign-bit inverted by inverter 601.

FIG. 7 shows a third embodiment where register 701 holds the real part of SRC1, and register 702 holds the imaginary part of SRC1. Similarly, the real part of SRC2 is held in register 703, and the imaginary part is in register 704. As shown on FIG. 7, the real part of SRC1 is multiplied by the real part of SRC2, and the imaginary part of SRC1 is multiplied by the imaginary part of SRC2 using floating point multipliers 705 through 708. Registers 709 and 714 hold the result from floating point multiplier 705, while registers 710 and 715 hold the output of floating point multiplier 707. Register 711 holds the result from floating point multiplier 706, and registers 712 and 717 hold the output of floating point multiplier 708. The content of register 711 is transferred to register 716 with the sign bit inverted by inverter 713.

At this point registers 714 through 717 hold the results of the four floating point multiplies, properly aligned to be further processed to form the final complex multiplication result. This sequence of operations is invoked by the CMPYSP instruction on the Texas Instruments c66x DSP.

To generate the final result floating point adder 718 sums the outputs of registers 714 and 716, while floating point adder 719 sums the outputs of registers 715 and 717. The output of floating point adder 718 is transferred to register 720 and forms the real part of the result. The output of floating point adder 719 is transferred to register 721 and forms the imaginary part of the result. This function is invoked by the DSP instruction DADDSP.

The assembly code for the DADDSP instruction on a Texas Instruments c66x DSP would be:

DADDSP A1:A0, A3:A2, A5:A4

where A0, A1, . . . A5 are 32 bit registers, each of which holds a 32 bit single precision floating point value. Instruction DADDSP performs two single precision floating point adds, adding A1 and A1, placing the result into A5, and adding A0 and A2, placing the result in A4. 

1. A complex multiplier circuit comprising of: a plurality of floating point multipliers, each operable to multiply two 32 bit single precision floating point operands SRC1 and SRC2 generating a result, and a plurality of floating point adders, each operable to add two floating point operands SRC1 and SRC2 generating a sum.
 2. The complex multiplier circuit of claim 1, wherein: the number of floating point multipliers is four.
 3. The complex multiplier circuit of claim 1, wherein: the number of floating point adders is two.
 4. The complex multiplier circuit of claim 1, wherein: the SRC1 and SRC2 inputs to the floating point multipliers are single precision floating point numbers, where each number represents the real or imaginary part of a complex number.
 5. The complex multiplier circuit of claim 1, wherein: SRC1 of the first floating point multiplier is the real part of the first operand, SRC2 of the first floating point multiplier is the real part of the second operand, SRC1 of the second floating point multiplier is the imaginary part of the first operand, SRC2 of the second floating point multiplier is the imaginary part of the second operand, SRC1 of the third floating point multiplier is the real part of the second operand, SRC2 of the third floating point multiplier is the imaginary part of the first operand, SRC1 of the fourth floating point multiplier is the imaginary part of the second operand, and SRC2 of the fourth floating point multiplier is the real part of the first operand.
 6. The complex multiplier circuit of claim 1, wherein: SRC1 of the first floating point adder is the result from the first floating point multiplier, SRC2 of the first floating point adder is the result from the second floating point multiplier, SRC1 of the second floating point adder is the result from the third floating point multiplier, and SRC2 of the second floating point adder is the result from the fourth floating point multiplier.
 7. The complex multiplier circuit of claim 6, wherein: bit 31 of the SRC2 input to the first floating point adder is inverted.
 8. The complex multiplier circuit of claim 6, wherein: the sum of the first floating point adder is the real part of the result of the complex multiply, and the sum of the second floating point adder is the imaginary part of the result of the complex multiply. 